1. Field of the Invention
This invention relates to a microcomputer which is equipped with the function of time shared parallel processing of plural programs.
2. Description of the Related Arts
Some of the recent microcomputers are designed to perform a time shared parallel processing of plural tasks by changing over the multi task processing in consecutive order by means of a register counter or a multiplexer as described, for instance, in the Japanease Patent Publication laid-open No. 58-155406, and No. 59-191654. In those conventional compositions, an exclusive hard timer is required to perform time processing by letting the elapsed time known when a task is executed. In addition, it is necessary to provide externally a runaway monitoring logic like a watchdog timer to monitor the runaway of program of each task, which contributes, combined with the above-mentioned matter, to making the peripheral circuits of a microcomputer complicated, leading to the product becoming larger-sized and more expensive.
Furthermore, in the conventional compositions, an erroneous jump to the address of other task and the execution of its instruction occurs due to an unexpected cause like noise. In the past, a reset method employed in such a case has been to provide a runaway monitoring logic such as a watchdog timer in the peripheral circuits, which involves time loss before a runaway is detected since it has to be monitored externally, and a risk of the memory data or port data being destroyed in the meantime.
Furthermore, the pipeline processing in the conventional microcomputers has the problem of there occurring pipeline disturbances when a branch instruction is executed, causing at least one wasteful cycle, i.e. delayed cycle, thereby delaying the pipeline processing. The cause of this wasteful cycle occurring after a branch instruction in the conventional pipeline processing is that if the branch instruction is fetched, the instruction address to be fetched next is predetermined in order beforehand regardless of the branch address, and the instruction of the branch address can be fetched only after this wasteful instruction is fetched.
In the past, it has been possible that the multiple-word instruction system with an unfixed number of instruction words, e.g. instruction system in which there are one-word instruction as well more than two-word instruction, can interpret an instruction wrongly due to mis-perception of the operation code or operand, thereby causing a program runaway or mass destruction of important information in data memory.
It is further possible for the program address to branch out to the address in the table immediate data area provided in the program memory, and an execution is started by perceiving the table immediate data as operation code, which also causes a program runaway or mass destruction of important information in data memory. On this account, it has been also necessary, in the past, to install a runaway monitoring logic such as a watchdog timer in the peripheral circuits, which contributes to making the peripheral circuits of a microcomputer complicated, resulting in the product becoming larger-sized and more expensive. Furthermore, the installation of a runaway monitoring logic such as a watchdog timer involves time loss before a runaway is detected since it has to be monitored externally, and a risk of the memory data or port data being destroyed in the meantime.